A 2GHz 13

Two’s complement multipliers are performance and power-critical components for wireless baseband signal processing applications. Parallel clusters of multiplier, multiply-add, multiply-accumulate cores are required to perform complex filter operations in Fast Fourier Transform (FFT) accelerators while consuming ultra low energy/operation [1]. A 12x9b single-cycle two’s complement twiddle multiplier for FFT acceleration implemented in 90nm dual-Vt CMOS technology [2], operating at 2GHz and consuming 13.6mW at 1.3V, 110°C is presented. Optimally tiled compressor tree architecture with radix-4 Booth encoding, arrival-profile aware completion adder and low clock power write-port flip-flop circuits enable this aggressive powerperformance by achieving (i) low compressor tree fanouts and wiring complexity, (ii) low active leakage power of 1.3mW and high noise tolerance with all highVt usage, (iii) scalable multiplier performance up to 2.5GHz, 33mW at 1.7V, 110°C, and (iv) low-voltage mode multiplier performance of 35MHz, 50μW at a supply of 300mV, 110°C.